1. Field of Invention
The invention is generally directed to the mass production of semiconductor devices. The invention is more specifically directed to the problem of tightening statistical variation of critical performance parameters during mass production of semiconductor devices, where the fabrication process includes TCI (Tilted Channel Implant) doping.
2a. Cross Reference to Issued Patents
The disclosures of the following U.S. patents are incorporated herein by reference:
(A) U.S. Pat. No. 5,926,690 issued Jul. 20, 1999 to Toprac, et al, and entitled, Run-to-run Control Process for Controlling Critical Dimensions; and
(B) U.S. Pat. No. 5,863,824 issued Jan. 26, 1999 to Gardner, et al, and entitled, Method of Forming Semiconductor Devices Using Gate Electrode Length and Spacer Width for Controlling Drive Current Strength.
2b. Description of Related Art
A mass-production tolerance problem emerges as the historically-consistent, and industry-pervasive, shrinkage for the effective length (Leff) of transistor channels continues on to smaller and smaller dimensions. Statistical variations tend to crop up over time in the mass-production processes that ultimately define effective channel length (Leff). Of importance, such statistical variations show up in what may termed as critical dimensions (CD""s) of in-process structures.
More specifically, it is predicted that shrinkage of dimensions will continue as it had in the past, with the implementation of ever smaller dimensions of channel length, such as moving from devices with channel lengths of about 0.25xcexc (0.25 micron) or less, down to devices with channel lengths of about 0.18xcexc or less, and then continuing down to devices with channel lengths of about 0.09xcexc or less, and perhaps continuing to even substantially smaller dimensions. As these dimensions shrink, the so-called critical dimensions"" (CD""s) of transistor-precursor structures (which structures appear during mass-production) become more and more difficult to control with precision. At the same time, the mass-production replication of such CD""s becomes more significant to final device performance as channel length dimensions shrink. New methods are needed for providing tighter process control of critical performance parameters so that desired statistical mean and 3 sigma (3"sgr") values can be obtained for mass-produced devices.
One factor that can play a substantial role in determining the ultimate Leff of each individual one of mass-produced transistors is the precision with which the actual length of the patterned gate material (e.g., polysilicon) can be controlled. This patterned gate material is that which remains in the transistor-precursor structure after completion of mass-production photomasking, mass-production resist trimming, and mass-production gate-material etch.
Another factor that can play a role in determining the ultimate Leff, in cases where sidewall spacers are formed and trimmed about the post-etch gate, is the precision to which the deposition and trimming of such sidewalls is carried out.
The interplay between such factors will become more apparent when the drawings are described in detail below. For now, it is sufficient to understand how, in a conventional fabrication process, an ideal or target value (LGateT) is established for the final length of the gate material that remains after gate-layer etching. Due to statistical process variations, and even though the measured, actual gate length (the gate FICD) will tend to have an average or mean value that is close to the ideal or target value (LGateT), individually-sampled dice or wafers or lots will tend to exhibit gate FICD""s (Final Inspection measurements of Critical Dimension) that deviate by finite amounts from the target value. In other words, there will typically be a manufacturing tolerance error that may be expressed as:
eGate=LGateTxe2x88x92FICDxe2x80x83xe2x80x83{Eq. 1}.
The group of fabrication technicians and/or other personnel who are responsible for keeping the post-etch gate length (as measured by FICD) close to the established ideal or target value (LGateT), will typically define an allowed tolerance-range, e1xe2x89xa6eGatexe2x89xa6e2 (where e1 is typically less than zero while e2 is greater than zero). Nonconforming, post-etch wafers will usually be thrown away.
If, at a given time during production, a statistically significant number of FICD measurements begin to fall outside the predefined, allowed tolerance-range, e1xe2x89xa6eGatexe2x89xa6e2, then production might need to be temporarily halted to find out why there is an such an unusual increase in the number of nonconforming, post-etch wafers. Specialty personnel (e.g., gate-etch control engineers) may have to be called in to determine what, if any, fine tunings should be made to the gate-etch process to bring its statistical results (mean and 3"sgr" deviation) back to acceptable numbers.
This is risky business. Sometimes an observed set of extreme deviations is just a random coincidence and the correct response (as can be shown only by hindsight) is to leave the gate-etch process unchanged. If a fine-tuning is nonetheless applied, that tuning may itself, over time, cause an even larger number of wafers to fall outside the allowed tolerance-range, e1xe2x89xa6eGatexe2x89xa6e2.
Further downstream along the mass-production line, there may be a second group of fabrication personnel who are responsible for applying (depositing) and trimming down, gate sidewalls. This second group will face a similar dilemma. They will establish statistical mean and allowed deviation ranges for sidewall film thickness and trim-down distance. The allowed range may be expressed as, e3xe2x89xa6eSidewallxe2x89xa6e4, where eSidewall is the error between measured and target thickness dimensions for the gate sidewalls, and e3 is typically less than zero while e4 is greater than zero. Nonconforming, post-trim wafers may have to be thrown away or stripped and re-worked.
If a statistically significant number of sidewall-thickness measurements begin to come back as falling outside the allowed tolerance-range, e3xe2x89xa6eSidewallxe2x89xa6e4, then production might need to be temporarily halted. Specialty personnel (e.g., sidewall-deposition and trim control engineers) may have to be called in to determine what, if any, fine tunings should be made to the sidewall-deposition and/or sidewall-trim processes to bring their statistical results (mean and 3"sgr" deviation) back to acceptable numbers. Like the case involving fine tuning of the gate-etch process, fine tuning of the sidewall-deposition and/or sidewall-trim processes is risky business. Sometimes an observed set of extreme deviations is just a random coincidence and the correct response is to leave the sidewall-related processes unchanged. If a fine-tuning is nonetheless applied, that tuning may over time, push an even larger number of samples outside the allowed tolerance-range.
It is seen from the above that CD measurement practices and statistical analysis and response practices can produce dilemmas. On the one hand, semiconductor manufacturers want to obtain good yield of final product in as little time as possible. On the same hand, they want to avoid the costs of human intervention. On the other hand, they want to avoid the possible errors of human judgment that might come to play with constant, manually-determined fine tunings to each gate etch or sidewall deposition or sidewall trim process. To achieve the end result of avoiding judgment errors, it has been generally accepted that the gate FICD""s (measured critical dimensions) must be maintained within very tight tolerances, even if that goal leads to a throwing away of large numbers of post-etch wafers. But that means that yield suffers. It is a situation that leaves practitioners in a can""t-win dilemma. They can suffer yield loss by taking either choice, namely, (a) throwing away large numbers of wafers and not re-tuning the production line, or (b) re-tuning the production line and, in cases where the re-tune contains human error, losing productivity because of the human judgment error.
Practices in accordance with the present invention offer win/win alternatives, in other words, those that can help to automatically reclaim what were previously considered out-of-specification dice or wafers without placing production personnel on the horns of a lose/lose dilemma. The present invention can improve final yield while at the same time avoiding the possible errors of human judgment that might come to play with constant, manually-determined fine tunings to processes that affect critical dimensions.
Signals representing manufacturing tolerance errors in one or both of gate length (eGate) and sidewall thickness (eSidewall) are fed forward in accordance with the invention to a variable TCI process. The energy and/or dosage values used in the Tilted Channel Implant (TCI) process are automatically adjusted in response. The variability of the energy and/or dosage values provides additional controls which can be automatically fine-tuned in accordance with the invention to counter manufacturing tolerance errors that occur in mass-production defining of gate length and sidewall thickness. Such error feed forward methods may be used in accordance with the invention for improving mass-production statistical distribution of critical parameters in semiconductor devices.
An automated production system in accordance with the invention comprises: (a) a variable TCI process having at least one of variable energy and variable dosage capabilities; and (b) feed-forward means for feeding forward to the variable TCI process, error signals representing manufacturing tolerance errors in one or both of gate length (eGate) and sidewall thickness (eSidewall), wherein at least one of said, variable energy and variable dosage capabilities of the TCI process is adjusted in response to the fed-forward error signals (eGate, eSidewall) to counter the effects of the error.
A mass-production method in accordance with the invention comprises the steps of: (a) defining a target, statistical mean value (L2T) for gate length; (b) defining a target, statistical mean value (SwT) for thickness of gate sidewalls; (c) measuring error (L2Txe2x88x92L2M) in gate length of a production sample; (d) measuring error (SwMxe2x88x92SwT) in sidewall thickness of the production sample; (e) calculating an adjusted Tilted Channel Implant energy in response to the measured error in sidewall thickness; (f) calculating an adjusted Tilted Channel Implant dosage in response to the measured error in gate length; and (g) performing a Tilted Channel Implant operation on said production sample while using at least one of the adjusted energy and adjusted dosage during said TCI operation.
A machine-implemented and automated mass-production method in accordance with the invention uses a pre-defined target, statistical mean value (L2T) for gate length and a pre-defined target, statistical mean value (SwT) for thickness of gate sidewalls, and comprises the steps of: (a) collecting first data representing error (L2Txe2x88x92L2M) in gate length of respective production samples; (b) collecting second data representing error (SwMxe2x88x92SwT) in sidewall thickness of the production samples; (c) for each non-zero error in sidewall thickness, responsively calculating an adjustment in Tilted Channel Implant energy to be employed for the corresponding production sample; (d) for each non-zero error in gate length, responsively calculating an adjustment in Tilted Channel Implant dosage to be employed for the corresponding production sample; and (e) performing a Tilted Channel Implant operation on each of said production samples while using at least one of the corresponding energy adjustment and corresponding dosage adjustment during said performance of the TCI operation on each respective production sample that is indicated to have non-zero error in gate length or sidewall thickness.
A method in accordance with the invention for optimizing automated, feed-forward compensation for manufacturing tolerance errors in one or both of gate length (eGate) and sidewall thickness (eSidewall) comprises the steps of: (a) defining a target, statistical mean value (L2T) for gate length; (b) defining a target, statistical mean value (SwT) for thickness of gate sidewalls; (c) determining a target, statistical mean value (VTT or QTT) for a critical electrical characteristic of transistors manufactured to have said target gate length and said target sidewall thickness; (d) identifying first stray production samples that have a predefined first amount of error (L2Txe2x88x92L2M) in gate length; (e) experimentally determining an amount of adjustment in Tilted Channel Implant dosage that may be employed for the corresponding first stray production samples so as to bring the critical electrical characteristic of transistors manufactured from said first stray production samples into conformance with said target value (VTT or QTT) for the critical electrical characteristic; (f) defining a dosage adjustment interpolation function for use when second stray production samples are identified with gate length errors substantially close to said predefined first amount of error (L2Txe2x88x92L2M) in gate length; (g) identifying third stray production samples that have a predefined second amount of error (SwMxe2x88x92SwT) in sidewall thickness; (h) experimentally determining an amount of adjustment in Tilted Channel Implant energy that may be employed for the corresponding third stray production samples so as to bring the critical electrical characteristic of transistors manufactured from said third stray production samples into conformance with said target value (VTT or QTT) for the critical electrical characteristic; (i) defining an energy adjustment interpolation function for use when fourth stray production samples are identified with sidewall thickness errors substantially close to said predefined second amount of error (SwMxe2x88x92SwT in sidewall thickness; and (j) using at least one of said dosage and energy adjustment interpolation functions for establishing respective TCI dosage and energy when subjecting further production samples to Tilted Channel Implant.
A method for increasing the mass-production in-conformance range for one or both of a gate trimming process and a sidewall trimming process in accordance with the invention comprises the steps of: (a) defining TCI dosage and energy adjustment functions for use in response to respective detection of error (L2Txe2x88x92L2M) in gate length of production samples and of error (SwMxe2x88x92SwT) in sidewall thickness of production samples; and (b) in view of said TCI dosage and energy adjustment functions, expanding the allowed tolerance range that would have been otherwise used if said TCI dosage and energy adjustment functions had not been in place, the expanded tolerance range being at least one for ADICD-defined error in photoresist (PR) trimming, or for FICD-defined error in gate etching, or for measured error in sidewall layer deposition thickness, or for measured error in post-trim sidewall thickness.
Other aspects of the invention will become apparent from the below detailed description.